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| revision 2.4 256m double data rate synchronous dram A3S56D30ETP a3s56d40etp mar., 2009 256mb ddr sdram specification A3S56D30ETP a3s56d40etp zentel electronics corp. 6f-1, no. 1-1, r&d rd. ii, hsin chu science park, 300 taiwan, r.o.c. tel:886-3-579-9599 fax:886-3-579-9299
page 1/ 38 revision 2.4 mar., 2009 256m double data rate synchronous dram A3S56D30ETP a3s56d40etp description A3S56D30ETP is a 4-bank x 8,388,608-word x 8bit, a3s56d40etp is a 4-bank x 4,194,304-word x 16bit double data rate synchronous dram , with sstl _2 interface. all control and address signals are referenced to the rising edge of clk. input da ta is registered on both edges of data strobe ,and output data and data strobe are referenced on bo th edges of clk. the a3s56d30/40etp achieves very high speed clock rate up to 200 mhz . features - vdd=vddq=2.5v+ 0.2v (-5e, -5, -6) - double data rate architecture ; two data transfers per clock cycle. - bidirectional , data strobe (dqs) is transmitted/received with data - differential clock input (clk and /clk) - dll aligns dq and dqs transitions with clk transitions edges of dqs - commands entered on each positive clk edge ; - data and data mask referenced to both edges of dqs - 4 bank operation controlled by ba0 , ba1 (bank address) - /cas latency - 2.0 / 2.5 / 3.0 (programmable) ; burst length - 2 / 4 / 8 (programmable) burst type - sequential / interleave (programmable) - auto precharge / all bank precharge controlled by a10 - support concurrent auto-precharge - 8192 refresh cycles / 64ms (4 banks concurrent refresh) - auto refresh and self refresh - row address a0-12 / column address a0-9(x8) /a0-8(x16) - sstl_2 interface - package 400-mil, 66-pin thin small outline package (tsop ii) with 0.65mm lead pitch zentel electronics corporation reserve the right to change products or specification without notice. page 2/ 38 revision 2.4 mar., 2009 256m double data rate synchronous dram A3S56D30ETP a3s56d40etp clk, /clk : master clock cke : clock enable /cs : chip select /ras : row address strobe /cas : column address strobe /we : write enable a0-12 : address input ba0,1 : bank address input vdd : power supply vddq : power supply for output vss : ground vssq : ground for output dq0-15 : data i/o (x16) udm, ldm : write mask (x16) pin assignment (top view) 66-pin tsop dm : write mask (x8) dq0-7 : data i/o (x8) udqs, ldqs : data strobe (x16) dqs : data strobe (x8) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 vdd dq0 vddq dq1 dq2 vssq dq3 dq4 vddq dq5 dq6 vssq dq7 nc vddq ldqs nc vdd nc ldm /we /cas /ras /cs nc ba0 ba1 a10/ap a0 a1 a2 a3 vdd vss dq15 vssq dq14 dq13 vddq dq12 dq11 vssq dq10 dq9 vddq dq8 nc vssq udqs nc vref vss udm /clk clk cke nc a12 a11 a9 a8 a7 a6 a5 a4 vss 66pin tsop(ii) 400mil width x 875mil length 0.65mm lead pitch row a0-12 column a0-9 (x8) a0-8 (x16) vdd dq0 vddq nc dq1 vssq nc dq2 vddq nc dq3 vssq nc nc vddq nc nc vdd nc nc /we /cas /ras /cs nc ba0 ba1 a10/ap a0 a1 a2 a3 vdd vss dq7 vssq nc dq6 vddq nc dq5 vssq nc dq4 vddq nc nc vssq dqs nc vref vss dm /clk clk cke nc a12 a11 a9 a8 a7 a6 a5 a4 vss x8 x16 page 3/ 38 revision 2.4 mar., 2009 256m double data rate synchronous dram A3S56D30ETP a3s56d40etp pin function clk, /clk input clock: clk and /clk are differential clock inputs. all address and control input signals are sampled on the crossi ng of the positive edge of clk and negative edge of /clk. output (read) data is referenced to the crossings of clk and /clk (both directions of crossing). cke input clock enable: cke controls internal cloc k. when cke is low, internal clock for the following cycle is ceas ed. cke is also used to se lect auto / self refresh. after self refresh mode is started, cke becomes asynchronous input. self refresh is maintained as long as cke is low. /cs input chip select: when /cs is high, any command means no operation. /ras, /cas, /we input combination of /ras, /cas, /we defines basic commands. a0-12 input a0-12 specify the row / column address in conjunction with ba0,1. the row address is specified by a0-12. the column address is specified by a0-9(x8) and a0-8(x16). a10 is also used to indicate precharge option. when a10 is high at a read / write command, an auto precharge is performed. when a10 is high at a precharge command, all banks are precharged. ba0,1 input dq0-7 (x8), dq0-15 (x16), input / output dqs (x8) vdd, vss power supply power supply for the memory array and peripheral circuitry. vddq, vssq power supply vddq and vssq are supplied to the output buffers only. bank address: ba0,1 specifies one of four banks to which a command is applied. ba0,1 must be set with act, pre, read, write commands. data input/output: data bus data strobe: output with read data, input with write data. edge-aligned with read data, centered in write data. used to capture write data. for the x16, ldqs corresponds to the data on dq0-dq7; udqs correspond to the data on dq8-dq15 symbol type description dm (x8) input input data mask: dm is an input mask signal for write data. input data is masked when dm is sampled high along with that input data during a write access. dm is sampled on both edges of dqs. although dm pins are input only, the dm loading matches the dq and dqs loading. for the x16, ldm corresponds to the data on dq0-dq7; udm corresponds to the data on dq8-dq15. input / output vref input sstl_2 reference voltage. udqs, ldqs (x16) udm, ldm (x16) page 4/ 38 revision 2.4 mar., 2009 256m double data rate synchronous dram A3S56D30ETP a3s56d40etp type designation code this rule is applied to only synchronous dram family. block diagram /cs /ras /cas /we dm memory array bank #0 dq0 - 7 i/o buffer memory array bank #1 memory array bank #2 memory array bank #3 mode register control circuitry address buffer a0-12 ba0,1 clock buffer clk cke control signal buffer dqs buffer dqs dll /clk A3S56D30ETP zentel dram speed grade package type tp: tsop(ii) process generation function reserved for future use organization 2 n 3: x8 d dr synchronous dram density 56: 256m bits interface s:sstl_2 memory style (dram) a 3 s 56 d 3 0 e tp ?g5e 6: 166mhz @cl=3.0/2.5, and 133mhz @cl=2.0 5: 200mhz @cl=3.0, 166mhz @cl=2.5, and 133mhz @cl=2.0 5e: 200mhz @cl=3.0/2.5, and 133mhz @cl=2.0 g: green part page 5/ 38 revision 2.4 mar., 2009 256m double data rate synchronous dram A3S56D30ETP a3s56d40etp type designation code this rule is applied to only synchronous dram family. block diagram /cs /ras /cas /we udm, ldm memory array bank #0 dq0 - 15 i/o buffer memory array bank #1 memory array bank #2 memory array bank #3 mode register control circuitry address buffer a0-12 ba0,1 clock buffer clk cke control signal buffer dqs buffer udqs, ldqs dll /clk a3s56d40etp zentel dram speed grade package type tp: tsop(ii) process generation function reserved for future use organization 2 n 4: x16 d dr synchronous dram density 56: 256m bits interface s:sstl_2 memory style (dram) a 3 s 56 d 4 0 e tp ?g5e 6: 166mhz @cl=3.0/2.5, and 133mhz @cl=2.0 5: 200mhz @cl=3.0, 166mhz @cl=2.5, and 133mhz @cl=2.0 5e: 200mhz @cl=3.0/2.5, and 133mhz @cl=2.0 g: green part page 6/ 38 revision 2.4 mar., 2009 256m double data rate synchronous dram A3S56D30ETP a3s56d40etp basic functions the a3s56d30/40etp provides basi c functions, bank (row) activate, burst read / write, bank (row) precharge, and auto / self refresh. each command is defined by co ntrol signals of /ras, /cas and /we at clk rising edge. in addition to 3 signals, /cs , cke and a10 are used as chip select, refresh option, and precharge option, resp ectively. to know the detailed definition of commands, please see th e command truth table. /cs chip select : l=select, h=deselect /ras command /cas command /we command cke refresh option @refresh command a10 precharge option @precharge or read/write command clk define basic commands /clk activate (act) [/ras =l, /cas =/we =h] act command activates a row in an idle bank indicated by ba. read (read) [/ras =h, /cas =l, /we =h] read command starts burst read fr om the active bank indicated by ba. first output data appears after /cas latency. when a10 =h at this command, the bank is deactivat ed after the burst read (auto- precharge, reada ) write (write) [/ras =h, /cas =/we =l] write command starts burst write to the active bank indicated by ba. total data length to be written is set by burst length. when a10 =h at this comm and, the bank is deactivated after the burst write (auto-precharge, writea ) precharge (pre) [/ras =l, /cas =h, /we =l] pre command deactivates the active bank indicated by ba. this command also terminates burst read /write operation. when a10 =h at this comman d, all banks are deactivated (precharge all, prea ). auto-refresh (refa) [/ras =/cas =l, /we =cke =h] refa command starts auto-refresh cycle. refresh address including bank address are generated internally. after this command, the banks are precharged automatically. page 7/ 38 revision 2.4 mar., 2009 256m double data rate synchronous dram A3S56D30ETP a3s56d40etp command truth table h=high level, l=low level, v=valid , x=don't care, n=clk cycle number note: 1. applies only to read bursts with autoprecharge disabled; this command is undefined (and should not be used) for read bursts with autoprecharg e enabled, and for write bursts. 2. ba0-ba1 select either the base or the extended mode register (ba0 = 0, ba1 = 0 selects mode register;ba0=1 , ba1 = 0 selects extended mode register; other combinations of ba0-ba1 are reserved; a0-a12 provide the op-code to be written to the selected mode register. command mnemonic cke n-1 cke n /cs /ras /cas /we ba0,1 a10 /ap a0-9, 11-12 deselect desel h x h x x x x x x no operation nop h x l h h h x x x row address entry & bank activate act h h l l h h v v v single bank precharge pre h h l l h l v l x precharge all banks prea h h l l h l h x column address entry & write write h h l h l l v l v column address entry & write with auto-precharge writea h h l h l l v h v column address entry & read read h h l h l h v l v column address entry & read with auto-precharge reada h h l h l h v h v auto-refresh refa h h l l l h x x x self-refresh entry refs h l l l l h x x x self-refresh exit refsx l h h x x x x x x l h l h h h x x x burst terminate term h h l h h l x x x mode register set mrs h h l l l l l l v x note 1 2 page 8/ 38 revision 2.4 mar., 2009 256m double data rate synchronous dram A3S56D30ETP a3s56d40etp function truth table current state /cs /ras /cas /we address command action notes idle h x x x x desel nop l h h h x nop nop l h h l ba term illegal 2 l h l x ba, ca, a10 read / write illegal 2 l l h h ba, ra act bank active, latch ra l l h l ba, a10 pre / prea nop 4 ll lhx refa auto-refresh 5 ll l l op-code, mode- add mrs mode register set 5 row active h x x x x desel nop l h h h x nop nop l h h l ba term illegal l h l h ba, ca, a10 read / reada begin read, latch ca, determine auto-precharge l h l l ba, ca, a10 write / writea begin write, latch ca, determine auto-precharge l l h h ba, ra act bank active / illegal 2 l l h l ba, a10 pre / prea precharge / precharge all l l l h x refa illegal ll l l op-code, mode- add mrs illegal h x x x x desel nop (continue burst to end) l h h h x nop nop (continue burst to end) l h h l ba term terminate burst l h l h ba, ca, a10 read / reada terminate burst, latch ca, begin new read, determine auto- precharge 3 l h l l ba, ca, a10 write / writea illegal l l h h ba, ra act bank active / illegal 2 l l h l ba, a10 pre / prea terminate burst, precharge l l l h x refa illegal ll l l op-code, mode- add mrs illegal read(auto- precharge disabled) page 9/ 38 revision 2.4 mar., 2009 256m double data rate synchronous dram A3S56D30ETP a3s56d40etp function truth table (continued) current state /cs /ras /cas /we address command action notes h x x x x desel nop (continue burst to end) l h h h x nop nop (continue burst to end) l h h l ba term illegal l h l h ba, ca, a10 read / reada terminate burst, latch ca, begin read, determine auto-precharge 3 l h l l ba, ca, a10 write / writea terminate burst, latch ca, begin write, determine auto-precharge 3 l l h h ba, ra act bank active / illegal 2 l l h l ba, a10 pre / prea terminate burst, precharge l l l h x refa illegal ll l l op-code, mode- add mrs illegal h x x x x desel nop (continue burst to end) l h h h x nop nop (continue burst to end) l h h l ba term illegal l h l h ba, ca, a10 read / reada support concurrent auto-precharge l h l l ba, ca, a10 write / writea support concurrent auto-precharge l l h h ba, ra act bank active / illegal 2 l l h l ba, a10 pre / prea precharge / illegal 2 l l l h x refa illegal ll l l op-code, mode- add mrs illegal h x x x x desel nop (continue burst to end) l h h h x nop nop (continue burst to end) l h h l ba term illegal l h l h ba, ca, a10 read / reada support concurrent auto-precharge l h l l ba, ca, a10 write / writea support concurrent auto-precharge l l h h ba, ra act bank active / illegal 2 l l h l ba, a10 pre / prea precharge / illegal 2 l l l h x refa illegal ll l l op-code, mode- add mrs illegal write(auto- precharge disabled) read with auto-precharge write with auto-precharge page 10/ 38 revision 2.4 mar., 2009 256m double data rate synchronous dram A3S56D30ETP a3s56d40etp function truth table (continued) current state /cs /ras /cas /we address command action notes h x x x x desel nop (idle after trp) l h h h x nop nop (idle after trp) l h h l ba term illegal 2 l h l x ba, ca, a10 read / write illegal 2 l l h h ba, ra act illegal 2 l l h l ba, a10 pre / prea nop (idle after trp) 4 l l l h x refa illegal ll l l op-code, mode- add mrs illegal h x x x x desel nop (row active after trcd) l h h h x nop nop (row active after trcd) l h h l ba term illegal 2 l h l x ba, ca, a10 read / write illegal 2 l l h h ba, ra act illegal 2 l l h l ba, a10 pre / prea illegal 2 l l l h x refa illegal ll l l op-code, mode- add mrs illegal h x x x x desel nop l h h h x nop nop l h h l ba term illegal 2 l h l x ba, ca, a10 read / write illegal 2 l l h h ba, ra act illegal 2 l l h l ba, a10 pre / prea illegal 2 l l l h x refa illegal ll l l op-code, mode- add mrs illegal row activating write re- covering pre- charging page 11/ 38 revision 2.4 mar., 2009 256m double data rate synchronous dram A3S56D30ETP a3s56d40etp function truth table (continued) abbreviations: h=high level, l=low level, x=don't care ba=bank address, ra=row address, ca=column address, nop=no operation notes: 1. all entries assume that cke was high during th e preceding clock cycle a nd the current clock cycle. 2. illegal to bank in specified state; function may be legal in the bank indicated by ba, depending on the state of that bank. 3. must satisfy bus contention, bus turn around, write recovery requirements. 4. nop to bank precharging or in idle state. may precharge bank indicated by ba. 5. illegal if any bank is not idle. illegal = device operation and/or data-integrity are not guaranteed. current state /cs /ras /cas /we address command action notes refreshing h x x x x desel nop (idle after trc) l h h h x nop nop (idle after trc) l h h l ba term illegal l h l x ba, ca, a10 read / write illegal l l h h ba, ra act illegal l l h l ba, a10 pre / prea illegal l l l h x refa illegal ll l l op-code, mode- add mrs illegal h x x x x desel nop (row active after trsc) l h h h x nop nop (row active after trsc) l h h l ba term illegal l h l x ba, ca, a10 read / write illegal l l h h ba, ra act illegal l l h l ba, a10 pre / prea illegal l l l h x refa illegal ll l l op-code, mode- add mrs illegal mode register setting page 12/ 38 revision 2.4 mar., 2009 256m double data rate synchronous dram A3S56D30ETP a3s56d40etp function truth table for cke abbreviations: h=high level, l=low level, x=don't care notes: 1. cke low to high transition will re-enable clk and other inputs asynchronously. a minimum setup time must be satisfied before any command other than exit. 2. power-down and self-refresh can be entered only from the all banks idle state. 3. must be legal command. current state cke n-1 cke n /cs /ras /cas /we address action notes h x xxxx xinvalid 1 l h hxxx xexit self-refresh (idle after trc) 1 l h l h h h x exit self-refresh (idle after trc) 1 l h l h h l x illegal 1 l h lhlxxillegal 1 l h l l x x x illegal 1 l l xxxx xnop (maintain self-refresh) 1 h x xxxx xinvalid l h xxxx xexit power down to idle l l xxxx xnop (maintain self-refresh) h h xxxx xrefer to function truth table 2 h l l l l h x enter self-refresh 2 h l hxxx xenter power down 2 h l l h h h x enter power down 2 h l l h h l x illegal 2 h l lhlxxillegal 2 h l l l x x x illegal 2 l x xxxx xrefer to current state =power down2 h h xxxx xrefer to function truth table h l xxxx xbegin clk suspend at next cycle 3 l h xxxx xexit clk suspend at next cycle 3 l l xxxx xmaintain clk suspend any state other than listed above self- refreshing power down all banks idle page 13/ 38 revision 2.4 mar., 2009 256m double data rate synchronous dram A3S56D30ETP a3s56d40etp simplified state diagram row active idle pre charge power down read reada write writea power on act refa refs refsx ckel ckeh mrs ckel ckeh write read writea writea reada read pre reada reada pre pre prea power applied mode register set self refresh auto refresh active power down automatic sequence command sequence write read pre charge all mrs burst stop term page 14/ 38 revision 2.4 mar., 2009 256m double data rate synchronous dram A3S56D30ETP a3s56d40etp power on sequence before starting normal operation, the following power on sequence is necessary to prevent a sdram from damaged or multifunctioning. 1. apply vdd before or the same time as vddq 2. apply vddq before or at the same time as vtt & vref 3. maintain stable condition for 200us after stable power and clk, apply nop or dsel 4. issue precharge command for all banks of the device 5. issue emrs 6. issue mrs for the mode register and to reset the dll 7. issue 2 or more auto refresh commands 8. maintain stable condition for 200 cycle after these sequence, the ddr sdram is idle state and ready for normal operation. mode register burst length, burst type and /cas latency can be programmed by setting the mode register (mrs). the mode register stores these data until the next mrs command, which may be issued when all banks are in idle state. after tmrd from a mrs command, the ddr sdram is ready for new command. /cs /ras /cas /we a12-a0 /clk v clk ba0 ba1 r: reserved for future use 0no 1yes dll reset 0 sequential 1 interleaved burst type bt=0 bt=1 000 r r 001 2 2 010 4 4 011 8 8 100 r r 101 r r 110 r r 111 r r bl burst length /cas latency 000 r 001 r 010 2 011 3 100 r 101 r 110 2.5 111 r cl latency mode ba1ba0a12a11a10a9a8a7a6a5a4a3a2a1a0 000000dr0 bt ltmode bl page 15/ 38 revision 2.4 mar., 2009 256m double data rate synchronous dram A3S56D30ETP a3s56d40etp extended mode register dll disable / enable mode can be programmed by setting the extended mode register (emrs). the extended mode register stores these data until the next emrs command, which may be issued when all banks are in idle state. after tmrd from a emrs command, the ddr sdram is ready for new command. /cs /ras /cas /we a12-a0 v ba0 ba1 /clk clk ba1ba0a12a11a10a9a8a7a6a5a4a3a2a1a0 0100000000000 ds dd 0normal 1weak drive strength 0 dll enable 1dll disable dll disable page 16/ 38 revision 2.4 mar., 2009 256m double data rate synchronous dram A3S56D30ETP a3s56d40etp /cas latency burst length cl= 2 bl= 4 burst length a2 a1 a0 initial address bl sequential interleaved column addressing 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 - 0 0 - 0 1 - 1 0 - 1 1 - - 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 7 0 1 2 0 1 2 3 1 2 3 0 2 3 0 1 3 0 0 1 7 6 5 4 0 1 2 3 1 0 3 2 2 3 0 1 3 2 0 1 - - 1 1 2 1 0 3 4 5 6 3 2 1 0 1 0 1 0 8 4 2 command address dq y y read write dqs q0 q1 q2 q3 d0 d1 d2 d3 /clk clk page 17/ 38 revision 2.4 mar., 2009 256m double data rate synchronous dram A3S56D30ETP a3s56d40etp absolute maximum ratings dc operating conditions (ta=0 ~ 70 o c, unless otherwise noted) capacitance (ta=0 ~ 70 o c, vdd = vddq = 2.5v + 0.2v, vss = vssq = 0v, unless otherwise noted) min. max. ci(a) input capacitance, address pin vi=1.25v 1.3 2.5 pf ci(c) input capacitance, control pin f=100mhz 1.3 2.5 pf ci(k) input capacitance, clk pin vi=25mvrms 1.3 2.5 0.25 pf ci/o i/o capacitance, i/o, dqs, dm pin 2 4 1.3 pf 0.75 notes limit s symbol parameter test condition unit delta cap.(max.) min. typ. max. vdd supply voltage 2.3 2.5 2.7 v vd d q i/ o su p p ly vo lt a g e 2.3 2.5 2.7 v vref i/o reference volatage 0.49*vddq 0.5*vddq 0.51*vddq v vt t i/ o t e rmin a t io n vo lt a g e vref-0.04 vref vref+0.04 v vih(dc) input high voltage vref+0.15 vdd+0.3 v vil(dc) input low voltage -0.3 vref-0.15 v vin(dc) input voltage level, ck and /ck inputs -0.3 vddq+0.3 v vid(dc) input differential voltage, ck and /ck inputs 0.36 vddq+0.6 v il input leakage current, any input 0v page 19/ 38 revision 2.4 mar., 2009 256m double data rate synchronous dram A3S56D30ETP a3s56d40etp ac timing requirements min. max min. max min. max tac dq output access time from clk//clk -0.70 +0.70 -0.70 +0.70 -0.70 +0.70 ns tdqsck dqs output access time from clk//clk -0.6 +0.6 -0.6 +0.6 -0.60 +0.60 ns tch clk high level width 0.45 0.55 0.45 0.55 0.45 0.55 tck tcl clk low level width 0.45 0.55 0.45 0.55 0.45 0.55 tck cl=3.0 512512612ns cl=2.5512612612ns cl=2.0 7.5 12 7.5 12 7.5 12 ns tds input setup time (dq,dm) 0.4 0.4 0.45 ns tdh input hold time(dq,dm) 0.4 0.4 0.45 ns tipw control & address input pulse width (for each input) 2.2 2.2 2.2 ns tdipw dq and dm input pulse width (for each input) 1.75 1.75 1.75 ns thz data-out-high impedance time from clk//clk +0.70 +0.70 +0.70 ns 14 tlz data-out-low impedance time from clk//clk -0.70 +0.70 -0.70 +0.70 -0.70 +0.70 ns 14 tdqsq dq valid data delay time from dqs 0.40 0.40 0.45 ns thp clock half period tclmin or tchmin tclmin or tchmin tclmin or tchmin ns 20 tqh dq output hold time from dqs (per access) thp-tqhs thp-tqhs thp-tqhs ns tqhs data hold skew factor (for dqs & associated dq signals) 0.50 0.50 0.55 tdqss write command to first dqs latching transition 0.72 1.25 0.72 1.25 0.75 1.25 tck tdqsh dqs input high level width 0.35 0.35 0.35 tck tdqsl dqs input low level width 0.35 0.35 0.35 tck tdss dq s falling edge to c lk setup time 0.2 0.2 0.2 tc k tdsh dq s falling edge hold time from c lk 0.2 0.2 0.2 tc k tmrd mode register set command cycle time 2 2 2 tck twpres write preamble setup time 0 0 0 ns 16 twpst write postamble 0.4 0.6 0.4 0.6 0.4 0.6 tck 15 twpre write preamble max(0.25* tck, 1.5ns) max(0.25* tck, 1.5ns) 0.25*tck ns tis input setup time (address and control) 0.6 0.6 0.75 ns 19 tih input hold time (address and control) 0.6 0.6 0.75 ns 19 trpst read postamble 0.4 0.6 0.4 0.6 0.4 0.6 tck trpre read preamble 0.9 1.1 0.9 1.1 0.9 1.1 tck tck symbol ac characteristics parameter -5e notes -5 clk cycle time -6 unit (ta=0 ~ 70 o c, unless otherwise noted) page 20/ 38 revision 2.4 mar., 2009 256m double data rate synchronous dram A3S56D30ETP a3s56d40etp ac timing requirements(continues) min. max min. max min. max tras row active time 40 120,000 40 120,000 42 120,000 ns trc row cycle time(operation) 55 55 60 ns trfc auto ref. to active/auto ref. command period 70 70 72 ns trcd row to column delay 15 15 18 ns trp row precharge time 15 15 18 ns trrd act to act delay time 10 10 12 ns twr write recovery time 15 15 15 ns tdal auto precharge write recovery + precharge time tck 21 twtr internal write to read command delay 2 2 1 tck txsnr exit self ref. to non- read command 75 75 75 ns txsrd exit self ref. to -read command 200 200 200 tck txpnr exit power down to command 1 1 1 tck txprd exit power down to -read command 1 1 1 tck 18 trefi average periodic refresh interval 7.8 7.8 7.8 s17 -6 unit notes symbol ac characteristics parameter -5e -5 output load condition dq output timing measurement reference point v ref v ref dqs v out v ref 30pf 50 v tt =v ref zo=50 (ta=0 ~ 70 o c, unless otherwise noted) page 21/ 38 revision 2.4 mar., 2009 256m double data rate synchronous dram A3S56D30ETP a3s56d40etp notes 1. all voltages referenced to vss. 2. tests for ac timing, idd, and electr ical, ac and dc characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device ope ration are guaranteed for the full voltage range specified. 3. ac timing and idd tests may use a vil to vih swing of up to 1.5v in the test environment, but input timing is still referenced to vref (or to the cro ssing point for ck//ck), and paramete r specifications are guaranteed for the specified ac input levels under normal use conditions. the minimum slew rate for the input signals is 1v/ns in the range between vil(ac) and vih(ac). 4. the ac and dc input level specifications are as defined in the sstl_2 standard (i.e. the receiver will effectively switch as a result of the signal crossing the ac input level, and will remain in that state as long as the signal does not ring back above (below) the dc input low (high) level. 5. vref is expected to be equal to 0.5*vddq of the transmitting device, and to track variations in the dc level of the same. peak-to-peak noise on vref may not exceed + 2% of the dc value. 6. vtt is not applied directly to the device. vtt is a system supply for signal termination resistors, is expected to be set equal to vref, and must track variations in the dc level of vref. 7. vid is the magnitude of the difference between the input level on clk and the input level on /clk. 8. the value of vix is expected to equal 0.5*vddq of the transmitting device and must track variations in the dc level of the same. 9. enables on-chip refresh and address counters. 10. idd specifications are tested after the device is properly initialized. 11. this parameter is sampled. vddq = 2.5v+ 0.2v, vdd = 2.5v + 0.2v , f = 100 mhz, ta = 25 o c, vout(dc) = vddq/2, vout(peak to peak) = 25mv. dm inputs are groupe d with i/o pins - reflecting the fact that they are matched in loading (to facilitate trace matching at the board level). 12. the clk//clk input reference level (for timing referenced to clk//clk) is the point at which clk and /clk cross; the input reference level for si gnals other than clk//clk, is vref. 13. inputs are not recognized as valid until vref stabilizes. ex ception: during the period before vref stabilizes, cke< 0.3vddq is recognized as low. 14. t hz and tlz transitions occur in the same access time wi ndows as valid data transitio ns. these parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (hz), or begins driving (lz). 15. the maximum limit for this parameter is not a device limit. the device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 16. the specific requirement is that dqs be valid (high, low, or at some point on a valid transition) on or before this clk edge. a valid transition is defined as monotonic, a nd meeting the input slew rate specifications of the device. when no writes were previously in progress on the bus, dqs will be transitioning from high-z to logic low. if a previous write was in progress, dqs could be high, lo w, or transitioning from high to low at this time, depending on tdqss. 17. a maximum of eight auto refresh commands can be posted to any given ddr sdram device. 18. txprd should be 200 tclk in the condition of the unstable clk operation during the power down mode. 19. for command/address and ck & /ck slew rate > 1.0v/ns. 20. min (tcl,tch) refers to the smaller of the actual cloc k low time and the actual clock high time as provided to the device. 21. tdalminimum = (twr/tck) + (trp/tck). for each of the terms above, if not already an integer, round to the next highest integer. page 22/ 38 revision 2.4 mar., 2009 256m double data rate synchronous dram A3S56D30ETP a3s56d40etp /clk dqs tis tih vref clk valid data read operation tac tdqsck tcl tch tck tdqsq tqh trpre trpst dqs /clk clk tdqss tds tdh tdqsl tdqsh twpre write operation / tdqss=max. tdss twpres twpst dqs /clk clk tdqss tds tdh tdqsl tdqsh twpre write operation / tdqss=min. tdsh twpres twpst dq dq dq cmd & add. page 23/ 38 revision 2.4 mar., 2009 256m double data rate synchronous dram A3S56D30ETP a3s56d40etp the ddr sdram has four independent banks. each bank is activated by the act command with the bank addresses (ba0,1). a row is indicated by the row address a0-12. the minimum activation interval between one bank and the other bank is trrd. bank activate operational description the pre command deactivates the bank indicate d by ba0,1. when multiple banks are active, the precharge all command (prea,pre+a10=h) is availa ble to deactivate them at the same time. after trp from the precharge, an act comma nd to the same bank can be issued. precharge bank activation and precharge all (bl=8, cl=2) a precharge command can be issued at bl/2 from a read comma nd without data loss. precharge all command a0-9,11,12 a10 ba0,1 dq act xa xa 00 read y 0 00 act xb xb 01 pre trrd trcd 1 act xb xb 01 tras trp trcmin 2 act command / trcmin dqs qa0 bl/2 qa1 qa2 qa3 qa4 qa5 qa6 qa7 /clk clk page 24/ 38 revision 2.4 mar., 2009 256m double data rate synchronous dram A3S56D30ETP a3s56d40etp after trcd from the bank activation, a read command can be issu ed. 1st output data is available after the /cas latency from th e read, followed by (bl-1) consecu tive data when the burst length is bl. the start address is specified by a0-9(x8) /a0-8(x16), and the address sequence of burst data is defined by the burst type. a read command ma y be applied to any active bank, so the row precharge time (trp) can be hidden behind conti nuous output data by interleaving the multiple banks. when a10 is high at a read command, the au to-precharge (reada) is performed. any command(read,write,pre,act) to the same bank is inhibited till the internal precharge is complete. the internal precharge starts at the la ter time of either bl/2 after reada or tras after act. the next act command can be issued after trp fro m the internal precharge. read multi bank interleaving read (bl=8, cl=2) /clk command a0-9,11,12 a10 ba0,1 dq act xa xa 00 read y 0 00 read y 0 10 act xb xb 10 pre 0 00 trcd /cas latency burst length dqs qa0 clk qa1 qa2 qa3 qa4 qa5 qa6 qa7 qb0 qb1 qb2 qb3 qb4 qb5 qb7 qb8 page 25/ 38 revision 2.4 mar., 2009 256m double data rate synchronous dram A3S56D30ETP a3s56d40etp trcd trp bl/2 bl/2 + trp read with auto-precharge (bl=8, cl=2,2.5,3.0) (bl/2 determinant case) command a0-9,11,12 a10 ba0,1 dq act xa xa 00 read y 1 00 dqs /clk clk internal precharge start timing qa0 qa1 qa2 qa3 qa4 qa5 qa6 qa7 dq dqs qa0 qa1 qa2 qa3 qa4 qa5 qa6 qa7 cl=2 cl=2.5 0 1 2 3 4 5 6 7 8 9 10 11 12 dq dqs qa0 qa1 qa2 qa3 qa4 qa5 qa6 qa7 cl=3.0 tras page 26/ 38 revision 2.4 mar., 2009 256m double data rate synchronous dram A3S56D30ETP a3s56d40etp trcd trp bl/2 read with auto-precharge (bl=8, cl =2,2.5,3.0) (tras determinant case) command a0-9,11,12 a10 ba0,1 dq act xa xa 00 read y 1 00 dqs /clk clk internal precharge start timing qa0 qa1 qa2 qa3 qa4 qa5 qa6 qa7 dq dqs qa0 qa1 qa2 qa3 qa4 qa5 qa6 qa7 cl=2 cl=2.5 0 1 2 3 4 5 6 7 8 9 10 11 12 dq dqs qa0 qa1 qa2 qa3 qa4 qa5 qa6 qa7 cl=3.0 tras page 27/ 38 revision 2.4 mar., 2009 256m double data rate synchronous dram A3S56D30ETP a3s56d40etp after trcd from the bank activatio n, a write command can be issued. 1st input data is set from the write command with data str obe input, following (bl-1) da ta are written into ram, when the burst length is bl. the start address is specified by a0-9(x8)/a0-8(x16), and the address sequence of burst data is defined by the burst type. a write command ma y be applied to any active bank, so the row precharge time (trp) can be hidden behind continuous input data by interleaving the multiple banks. from the last da ta to the pre command, the write recovery time (twr) is required. when a10 is high at a write command, the auto-precharge(writea) is performed. any comma nd(read,write,pre,act) to the same bank is inhibited till the internal precharge is complete. the next ac t command can be issued at the later time of either tdal from the last input data cycle or trc after act. write multi bank interleaving write (bl=8) command a0-9,11,12 a10 ba0,1 dq act xa 00 write 00 write 0 0 10 act xb 10 0 10 trcd d trcd d pre xa 0 00 pre dqs /clk clk da0 da1 da2 da3 da4 da5 da6 da7 db0 db1 db2 db3 db4 db5 db6 db7 xa ya yb xb page 28/ 38 revision 2.4 mar., 2009 256m double data rate synchronous dram A3S56D30ETP a3s56d40etp write with auto-precharge (bl=8) (tdal determinant case) command a0-9,11,12 a10 ba0,1 dq act xa 00 write 1 00 act xb 00 trcd d da0 dqs /clk clk da1 da2 da3 da4 da5 da6 da7 tdal xa y xb 0 1 2 3 4 5 6 7 8 9 10 11 12 trc write with auto-precharge (bl=8) (trc determinant case) command a0-9,11,12 a10 ba0,1 dq act xa 00 write 1 00 act xb 00 trcd d da0 dqs /clk clk da1 da2 da3 da4 da5 da6 da7 tdal xa y xb 0 1 2 3 4 5 6 7 8 9 10 11 12 trc page 29/ 38 revision 2.4 mar., 2009 256m double data rate synchronous dram A3S56D30ETP a3s56d40etp burst interruption [read interrupted by read] burst read operation can be interrupted by new r ead of any bank. random co lumn access is allowed. read to read interval is minimum 1clk. read interrupted by read (bl=8, cl=2) command a0-9 a10 ba0,1 dq yi read read read read yj yk yl 0 0 0 0 00 10 00 01 dqs qai0 qai1 qaj0 qaj1 qaj2 qaj3 qak0 qak1 qak2 qak3 qak4 qak5 qal0 qal1 qal2 qal3 qal4 qal5 qal6 qal7 /clk clk [read interrupted by precharge] burst read operation can be interrupted by prechar ge of the same bank. read to pre interval is minimum 1 clk. a pre co mmand to output disable latency is equivalent to the /cas latency. as a result, read to pre interval determines valid data length to be output. the figure below shows examples of bl=8. read interrupted by precharge (bl=8) cl=2.0 /clk clk command dqs command dq command dq q0 q1 q2 q3 q0 q1 dq q0 q1 q2 q3 q4 q5 pre read read pre read pre dqs dqs page 30/ 38 revision 2.4 mar., 2009 256m double data rate synchronous dram A3S56D30ETP a3s56d40etp read interrupted by precharge (bl=8) cl=2.5 command dqs command dq command dq q0 q1 q2 q3 q0 q1 /clk clk dq q0 q1 q2 q3 q4 q5 pre read read pre read pre dqs dqs read interrupted by precharge (bl=8) cl=3.0 /clk clk command dqs command dq command dq dq pre read read pre q0 q1 q2 q3 q4 q5 read pre dqs q0 q1 q2 q3 dqs q0 q1 page 31/ 38 revision 2.4 mar., 2009 256m double data rate synchronous dram A3S56D30ETP a3s56d40etp burst read operation can be interrupted by a bu rst stop command(term). read to term interval is minimum 1 clk. a term command to output disable latency is equivalent to the /cas latency. as a result, read to term interval determines valid data length to be output. the figure below shows examples of bl=8. [read interrupted by burst stop] read interrupted by term (bl=8) /clk clk cl=2.5 command dqs command dq command dq q0 q1 q2 q3 q0 q1 dq q0 q1 q2 q3 q4 q5 term read read term read term dqs dqs cl=2.0 command dqs command dq command dq q0 q1 q2 q3 q0 q1 dq q0 q1 q2 q3 q4 q5 term read read term read term dqs dqs page 32/ 38 revision 2.4 mar., 2009 256m double data rate synchronous dram A3S56D30ETP a3s56d40etp [read interrupted by write with term] read interrupted by term (bl=8) /clk clk cl=2.5 command dq q0 q1 q2 q3 read term dqs write d 0 d1 d2 d3 d4 d5 cl=2.0 command dq q0 q1 q2 q3 read term dqs write d0 d1 d2 d3 d4 d5 d6 d7 read interrupted by term (bl=8) /clk clk cl=3.0 command dqs command dq command dq dq term read read term q0 q1 q2 q3 q4 q5 read term dqs q0 q1 q2 q3 dqs q0 q1 cl=3.0 command dq q0 q1 q2 q3 read term dqs write d0 d1 d2 d3 d4 d5 page 33/ 38 revision 2.4 mar., 2009 256m double data rate synchronous dram A3S56D30ETP a3s56d40etp burst write operation can be interrupted by write of any bank. random colu mn access is allowed. write to write interval is minimum 1 clk. [write interrupted by write] [write interrupted by read] burst write operation can be interrupted by read of the same or the other bank. random column access is allowed. internal write to read command interval(t wtr) is minimum 1 clk. the input data on dq at the interrup ting read cycle is "don't care". twt r is referenced from the first positive edge after the last data input. write interrupted by read (bl=8, cl=2.5) command a0-9 a10 ba0,1 dq write yi 0 00 read yj 0 00 dai0 dai1 qaj0 qaj1 qaj2 qaj3 qs qaj4 qaj5 qaj6 qaj7 dm twtr /clk clk write interrupted by write (bl=8) command a0-9 a10 ba0,1 write yi 0 00 write yk 0 10 write yj 0 00 write yl 0 00 dq dai1 daj1 daj3 dak1 dak3 dak5 dal1 dqs dal2 dal3 dal5 dal6 dal7 dal4 dal0 dak4 dak2 dak0 dai0 daj0 daj2 /clk clk page 34/ 38 revision 2.4 mar., 2009 256m double data rate synchronous dram A3S56D30ETP a3s56d40etp burst write operation can be interrupted by prech arge of the same or all bank. random column access is allowed. twr is referenced from the first positive clk edge after the last data input. [write interrupted by precharge] write interrupted by precharge (bl=8, cl=2.5) command a0-9 a10 ba0,1 dq write yi 0 00 pre 00 dai0 dai1 qs dm twr /clk clk page 35/ 38 revision 2.4 mar., 2009 256m double data rate synchronous dram A3S56D30ETP a3s56d40etp [initialize and mode register sets] command /clk clk emrs pre nop mrs pre ar ar mrs act code code xa code xa 1 0 xa a0-12 a10 code 1 ba0,1 dqs dq 1 0 0 0 0 code tmrd tmrd trp trfc trfc tmrd mode register set, reset dll extended mode register set [auto refresh] single cycle of auto-refresh is initiated with a refa(/cs=/ra s=/cas=l,/we=cke=h) command. the refresh address is generated inte rnally. 8192 refa cycles within 64ms refresh 256mbits memory cells. the auto-refresh is perfor med on 4 banks concurrently. before performing an auto refresh, all banks must be in the idle stat e. auto-refresh to auto-refre sh interval is minimum trfc . any command must not be supplied to the device before trfc from the refa command. auto-refresh /ras cke /cs /cas /we a0-12 ba0,1 nop or deselect trfc auto refresh on all banks auto refresh on all banks /clk clk cke initialize and mrs page 36/ 38 revision 2.4 mar., 2009 256m double data rate synchronous dram A3S56D30ETP a3s56d40etp [self refresh] self -refresh mode is entered by issuing a refs command (/cs=/ras=/cas=l,/we=h,cke=l). once the self-refresh is initiated, it is maintained as long as cke is kept low. during the self- refresh mode, cke is asynchronous and the only enable input, al l other inputs including clk are disabled and ignored, so that power consumpti on due to synchronous inputs is saved. to exit the self-refresh, supplying stable cl k inputs, asserting desel or nop command and then asserting cke for longer than txsnr/txsrd. self-refresh /ras cke /cs /cas /we a0-12 ba0,1 txsnr self refresh exit /clk clk x y x y txsrd page 37/ 38 revision 2.4 mar., 2009 256m double data rate synchronous dram A3S56D30ETP a3s56d40etp the purpose of clk suspend is power down. cke is synchronous input except during the self- refresh mode. a command at cycl e is ignored. from cke=h to nor mal function, dll recovery time is not required in the condition of the stab le clk operation during the power down mode. [power down] /clk clk power down by cke command pre cke command act cke standby power down nop nop valid nop nop valid active power down dm is defined as the data mask for writes. du ring writes,dm masks input data word by word. dm to write mask latency is 0. [dm control] dm function(bl=8,cl=2) command dqs dq dm write read d0 d1 d3 d4 d5 d6 d7 masked by dm=h don't care q2 q3 q4 q5 /clk clk q0 q1 q6 txpnr/txprd page 38/ 38 revision 2.4 mar., 2009 256m double data rate synchronous dram A3S56D30ETP a3s56d40etp zentel dram products are not intended for medi cal implementation, airplane and transportation instrument, safety equipments, or any other app lications for life support or where zentel products failure could result in life loss, personal inju ry, or environment damage. zentel customers who purchase zentel products for use in such applications do so in their own risk and fully agree zentel accepts no liability for any damage from this improper use. important notice : |
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